夏宇聞

Overview

Works:	2 works in 1 publications in 1 languages

Titles

Verilog HDL数字设计与综合 by: Palnitkar,, Samir; 刁嵐松; 夏宇聞; 巴尼卡 ((Palnitkar, Samir)); 胡燕祥 (Language materials, printed) , [譯]

Subjects

電腦 VHDL語言